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TC62D776CFNAG 2011-12-14 1 toshiba cdmos integrated circuit silicon monolithic TC62D776CFNAG 16-channel constant-current led driver of the 3.3-v and 5-v power supply the TC62D776CFNAG is a constant-current driver for led and led display lighting applications. the output current from each of the 16 outputs is programmable via a single external resistor. the TC62D776CFNAG contains a 16-channel shift register, a 16-channel latch, a 16-channel and gate and a 16-channel constant-current output. fabricated with a cmos process, the TC62D776CFNAG allows high-speed data transfer. it operates with a 3.3- or 5-v power supply. . features supply voltage : v dd = 3.0~5.5 v 16-output built-in output current setup range : i out = 1.5~90 ma constant current output accuracy (@ r ext = 1.2 k , v out = 1.0 v, v dd = 3.3 v, 5.0 v) : s rank; between outputs 1.5 % (max) : s rank; between devices 1.5 % (max) : n rank; between outputs 2.5 % (max) : n rank; between devices 2.5 % (max) output voltage : v out = 17 v (max) i/o interface : cmos inte rfaces (schmitt trigger input) data transfer frequency : f sck = 25 mhz (max) operation temperature range : t opr = ? 40~85 c 8-bit (256 steps) current correction function built-in. 1 bit (hc) by the msb side: selects the output current range. 7 bit by the lsb side: output current is adjusted at 128 st eps in the range of 11% to 45%. (in the case of hc=1) output current is adjusted at 1 28 steps in the range of 50% to 200%. (in the case of hc=0) thermal shutdown function (tsd) built-in. output error detection function built-in. auto-output error detection and manual -output error detection using commands output open detection function (ood) and out put short detection function (osd) built-in. power-on-reset function built-in. (when the power supply is turned on, internal data is reset) stand-by function built-in. (i dd = 1 a at standby mode) output delay function built-in. (o utput switching noise is reduced) package : p-ssop24-0409-0.64-001 for detailed part naming conventions, contact your local toshiba sales representative or distributor. p-ssop24-0409-0.64-001 weight : 0.14g (typ.)
TC62D776CFNAG 2011-12-14 2 block diagram out0 trans enable out1 out15 tsd circuit reference voltage circuit error detection circuit constant current output circuit command control circuit on/off data register data transfer control circuit state setting register error detection result data register sin sck 16-bit shift registor sout selection circuit f/f por circuit 8bit dac r-ext sout 16 16 16 16 output delay circuit vdd gnd pin assignment (top view) gnd sin trans sck out0 out1 out2 out3 vdd r-ext sout enable out7 out6 out5 out4 10out 9out 8out 11out 12out 15out 14out 13out
TC62D776CFNAG 2011-12-14 3 terminal description pin no. pin name function 1 gnd gnd terminal 2 sin serial data input terminal 3 sck serial data transfe r clock input terminal 4 trans data transfer command input terminal 5 out0 constant-current output terminal 6 out1 constant-current output terminal 7 2out constant-current output terminal 8 out3 constant-current output terminal 9 out4 constant-current output terminal 10 out5 constant-current output terminal 11 out6 constant-current output terminal 12 out7 constant-current output terminal 13 8out constant-current output terminal 14 9out constant-current output terminal 15 10out constant-current output terminal 16 11out constant-current output terminal 17 12out constant-current output terminal 18 13out constant-current output terminal 19 14out constant-current output terminal 20 15out constant-current output terminal 21 enable an output current enable signal input terminal in "h" level input, outputs are turned off compulsorily. in "l" level input, outputs are on/off controlled according to serial data. 22 sout serial data output terminal. 23 r-ext an external resistance for an output current setup is connected between this terminal and ground. 24 vdd power supply terminal
TC62D776CFNAG 2011-12-14 4 equivalent circuits for inputs and outputs 1. enable terminal 2. trans terminal sck and sin terminals 3. sout terminal 4. out0 to out15 terminals vdd enable gnd r (up) vdd gnd r (down) trans sck sin vdd gnd vdd gnd serial-out gnd out0 ~ 15out
TC62D776CFNAG 2011-12-14 5 timing diagram the TC62D776CFNAG can operate with a 3. 3- or 5.0-v power supply. the same voltage must be supplied to the power and signal (sck/sin/trans/ enable ) domains. sin trans sck out0 out1 sout enable 15out 2out h l n = 0 1 2 3 4 5 6 8 h l h l h l on off on off on off on off h l 7911 10 12 13 1514
TC62D776CFNAG 2011-12-14 6 the explanation of the function (basic data input pattern) data is serially loaded into the TC62D776CFNAG using the sin and sck inputs. command selection is done via the sck and trans inputs. about the operation of each command symbol num of sck at trans=?h? (note2) operation s0 0,1 input of output on/off data. s1 5,6 executes output open/short detection manually. (note1) transfers the result of open/short detecti on to the 16-bit shift register. (note1) s2 7,8 input of state setting data (1). s3 9,10 input of state setting data (2). note 1: when output open/short detection is enabled. note 2: sck pulse trains other than those shown above are not recognized as commands. ? s0 command (input of output on/off data.) sck trans sin output on/off data ? s1 command (output open/short detection function manual operation is executed.) ? s2 command (input of state setting data (1).) ? s3 command (input of state setting data (2).) the number of sck pulses at trans="h" is 0 or 1. the number of sck pulses at trans="h" is 5 or 6 the number of sck pulses at trans="h" is 7 or 8 the number of sck pulses at trans="h" is 9 or 10
TC62D776CFNAG 2011-12-14 7 about the operation of each command s0 command (input of output on/off data.) description if sck pulses high zero or one time while trans is hi gh, it is interpreted as the s0 command, which acts as follows. basic input pattern of s0 command input form of output on/off data msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 15out 14out 13out 12out 11out 10out 9out 8out out7 out6 out5 out4 out3 2out out1 out0 input in msb first. output on/off data setting input data setting 1 output turn on 0 output turn off default after power-on data setting 0 output turn off automatic error detection mode if output open/short detection is enabled, its result is automatically transferred from the error detection result register to the 16-bit shift register, which can be shifted out from the sout pin. output open/short detection can be enabled with the s3 command. open/short errors can be detected only for output channel s that are enabled for at least 800 ns (note 1) and are configured to be turned on. for the disabled output channels, the detection result will be 1 (normal). if the output channels stay on for no longer than 800 ns, the autom atic error detection result will be invalid; in this case, the detection results of all channels will be 1 (normal). note 1: automatic error detection is triggered by the falling edge of the enable signal. thus, this feature can not be used when enable is tied low. in the figure shown below, the outputs are enabled for over 800 ns during the terr2 period, but the automatic error detection result is invalid; thus, it should be kept in mind that the detection results will be 1 (normal) for all channels.
TC62D776CFNAG 2011-12-14 8 output form of output opening/ short detection result data the result of output open/short detecti on is transferred to the 16-bit shift register in the format shown below. msb lsb e15 e14 e13 e12 e11 e10 e9 e8 e7 e6 e5 e4 e3 e2 e1 e0 15out 14out 13out 12out 11out 10out 9out 8out out7 out6 out5 out4 out3 2out out1 out0 error code (when output open detection function is effective) judging in error detection error code condition of output terminal v ood v out 0 open v ood v out 1 normal error code (when output open/short detection function is effective) judging in error detection error code condition of output terminal v ood v out or v osd v out 0 open or short-circuit v ood v out 1 normal *when both output error detection function is effe ctive, open and short-circ uit are undistinguishable. basic input pattern of s0 command when output opening/short detection is effective. 9? after the s0 command is loaded, the first sck pulse (m arked x above) is used to transfer an error detection result to the 16-bit shift register. at this time, the TC62D776CFNAG ignores the sin input.
TC62D776CFNAG 2011-12-14 9 s1 command (output open/short detection function manual operation is executed.) description if sck pulses high five or six times while trans is high, it is interpreted as the s1 command, which acts as follows. if output open/short detection is enabl ed, a current of approximately 60 a is forced to flow to all the outputs during the t on(s1) period in order to perform open/short detection. t on(s1) is approximately 800 ns long. its result is immediately transferred to the 16-bit shif t register, which can be shifted out from the sout pin. the format used to transfer the detection result is the same as for the s0 command. output open/short detection can be enabled with the s3 command. note: the s1 command should be loaded when the outputs are off. the s1 command is not executed if it is loaded when enable = low.the s1 command is not also exec uted when output open/short detection is disabled. sck should not be applied during the t on(s1) period. basic input pattern of s1 command after the s1 command is loaded, the first sck pulse (m arked x above) is used to transfer an error detection result to the 16-bit shift register. at this time, the TC62D776CFNAG ignores the sin input.
TC62D776CFNAG 2011-12-14 10 s2 command (input of state setting data (1).) description if sck pulses high seven or eight times while trans is high, it is interpreted as the s0 command, which acts as follows. the TC62D776CFNAG transfers the stat e control data (1) from the 16-bit shift register to the state control register. the states that can be programmed with the s2 command are shown below. basic input pattern of s2 command) input form of state setting data (1) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 r0 s0 t0 u0 - - h0 l0 *input in msb first. *please input "l" data to d7~d2. state setting data (1) setting input data setting bit outline of command 0 1 default after power-on a7 setting of current correction range high set mode 50%~200% low set mode 11%~45% high set mode 50%~200% a6~a0 setting of current correction data refer to attached table. 100% r0~u0 test mode setting. please input "l" data. "l" h0 data initialization normal initialization normal l0 setting of standby mode (1) normal active normal
TC62D776CFNAG 2011-12-14 11 details of each setting a setting (setting of current correction data) 1. in the case of a high setting mode (50%~200%) a[6] a[5] a[4] a[3] a[2] a[1] a[0] current gai n(%) a[6] a[5] a[4] a[ 3] a[2] a[1] a[0] current gain(%) 1 1 1 1 1 1 1 200.00 0 1 1 1 1 1 1 124.41 1 1 1 1 1 1 0 198.82 0 1 1 1 1 1 0 123.23 1 1 1 1 1 0 1 197.64 0 1 1 1 1 0 1 122.05 1 1 1 1 1 0 0 196.46 0 1 1 1 1 0 0 120.87 1 1 1 1 0 1 1 195.28 0 1 1 1 0 1 1 119.69 1 1 1 1 0 1 0 194.09 0 1 1 1 0 1 0 118.50 1 1 1 1 0 0 1 192.91 0 1 1 1 0 0 1 117.32 1 1 1 1 0 0 0 191.73 0 1 1 1 0 0 0 116.14 1 1 1 0 1 1 1 190.55 0 1 1 0 1 1 1 114.96 1 1 1 0 1 1 0 189.37 0 1 1 0 1 1 0 113.78 1 1 1 0 1 0 1 188.19 0 1 1 0 1 0 1 112.60 1 1 1 0 1 0 0 187.01 0 1 1 0 1 0 0 111.42 1 1 1 0 0 1 1 185.83 0 1 1 0 0 1 1 110.24 1 1 1 0 0 1 0 184.65 0 1 1 0 0 1 0 109.06 1 1 1 0 0 0 1 183.46 0 1 1 0 0 0 1 107.87 1 1 1 0 0 0 0 182.28 0 1 1 0 0 0 0 106.69 1 1 0 1 1 1 1 181.10 0 1 0 1 1 1 1 105.51 1 1 0 1 1 1 0 179.92 0 1 0 1 1 1 0 104.33 1 1 0 1 1 0 1 178.74 0 1 0 1 1 0 1 103.15 1 1 0 1 1 0 0 177.56 0 1 0 1 1 0 0 101.97 1 1 0 1 0 1 1 176.38 0 1 0 1 0 1 1 100.79 (default) 1 1 0 1 0 1 0 175.20 0 1 0 1 0 1 0 99.61 1 1 0 1 0 0 1 174.02 0 1 0 1 0 0 1 98.43 1 1 0 1 0 0 0 172.83 0 1 0 1 0 0 0 97.24 1 1 0 0 1 1 1 171.65 0 1 0 0 1 1 1 96.06 1 1 0 0 1 1 0 170.47 0 1 0 0 1 1 0 94.88 1 1 0 0 1 0 1 169.29 0 1 0 0 1 0 1 93.70 1 1 0 0 1 0 0 168.11 0 1 0 0 1 0 0 92.52 1 1 0 0 0 1 1 166.93 0 1 0 0 0 1 1 91.34 1 1 0 0 0 1 0 165.75 0 1 0 0 0 1 0 90.16 1 1 0 0 0 0 1 164.57 0 1 0 0 0 0 1 88.98 1 1 0 0 0 0 0 163.39 0 1 0 0 0 0 0 87.80 1 0 1 1 1 1 1 162.20 0 0 1 1 1 1 1 86.61 1 0 1 1 1 1 0 161.02 0 0 1 1 1 1 0 85.43 1 0 1 1 1 0 1 159.84 0 0 1 1 1 0 1 84.25 1 0 1 1 1 0 0 158.66 0 0 1 1 1 0 0 83.07 1 0 1 1 0 1 1 157.48 0 0 1 1 0 1 1 81.89 1 0 1 1 0 1 0 156.30 0 0 1 1 0 1 0 80.71 1 0 1 1 0 0 1 155.12 0 0 1 1 0 0 1 79.53 1 0 1 1 0 0 0 153.94 0 0 1 1 0 0 0 78.35 1 0 1 0 1 1 1 152.76 0 0 1 0 1 1 1 77.17 1 0 1 0 1 1 0 151.57 0 0 1 0 1 1 0 75.98 1 0 1 0 1 0 1 150.39 0 0 1 0 1 0 1 74.80 1 0 1 0 1 0 0 149.21 0 0 1 0 1 0 0 73.62 1 0 1 0 0 1 1 148.03 0 0 1 0 0 1 1 72.44 1 0 1 0 0 1 0 146.85 0 0 1 0 0 1 0 71.26 1 0 1 0 0 0 1 145.67 0 0 1 0 0 0 1 70.08 1 0 1 0 0 0 0 144.49 0 0 1 0 0 0 0 68.90 1 0 0 1 1 1 1 143.31 0 0 0 1 1 1 1 67.72 1 0 0 1 1 1 0 142.13 0 0 0 1 1 1 0 66.54 1 0 0 1 1 0 1 140.94 0 0 0 1 1 0 1 65.35 1 0 0 1 1 0 0 139.76 0 0 0 1 1 0 0 64.17 1 0 0 1 0 1 1 138.58 0 0 0 1 0 1 1 62.99 1 0 0 1 0 1 0 137.40 0 0 0 1 0 1 0 61.81 1 0 0 1 0 0 1 136.22 0 0 0 1 0 0 1 60.63 1 0 0 1 0 0 0 135.04 0 0 0 1 0 0 0 59.45 1 0 0 0 1 1 1 133.86 0 0 0 0 1 1 1 58.27 1 0 0 0 1 1 0 132.68 0 0 0 0 1 1 0 57.09 1 0 0 0 1 0 1 131.50 0 0 0 0 1 0 1 55.91 1 0 0 0 1 0 0 130.31 0 0 0 0 1 0 0 54.72 1 0 0 0 0 1 1 129.13 0 0 0 0 0 1 1 53.54 1 0 0 0 0 1 0 127.95 0 0 0 0 0 1 0 52.36 1 0 0 0 0 0 1 126.77 0 0 0 0 0 0 1 51.18 1 0 0 0 0 0 0 125.59 0 0 0 0 0 0 0 50.00
TC62D776CFNAG 2011-12-14 12 2. in the case of a low setting mode (11%~45%) a[6] a[5] a[4] a[3] a[2] a[1] a[0] current gai n(%) a[6] a[5] a[4] a[ 3] a[2] a[1] a[0] current gain(%) 1 1 1 1 1 1 1 45.00 0 1 1 1 1 1 1 27.87 1 1 1 1 1 1 0 44.73 0 1 1 1 1 1 0 27.60 1 1 1 1 1 0 1 44.46 0 1 1 1 1 0 1 27.33 1 1 1 1 1 0 0 44.20 0 1 1 1 1 0 0 27.06 1 1 1 1 0 1 1 43.93 0 1 1 1 0 1 1 26.80 1 1 1 1 0 1 0 43.66 0 1 1 1 0 1 0 26.53 1 1 1 1 0 0 1 43.39 0 1 1 1 0 0 1 26.26 1 1 1 1 0 0 0 43.13 0 1 1 1 0 0 0 25.99 1 1 1 0 1 1 1 42.86 0 1 1 0 1 1 1 25.72 1 1 1 0 1 1 0 42.59 0 1 1 0 1 1 0 25.46 1 1 1 0 1 0 1 42.32 0 1 1 0 1 0 1 25.19 1 1 1 0 1 0 0 42.06 0 1 1 0 1 0 0 24.92 1 1 1 0 0 1 1 41.79 0 1 1 0 0 1 1 24.65 1 1 1 0 0 1 0 41.52 0 1 1 0 0 1 0 24.39 1 1 1 0 0 0 1 41.25 0 1 1 0 0 0 1 24.12 1 1 1 0 0 0 0 40.98 0 1 1 0 0 0 0 23.85 1 1 0 1 1 1 1 40.72 0 1 0 1 1 1 1 23.58 1 1 0 1 1 1 0 40.45 0 1 0 1 1 1 0 23.31 1 1 0 1 1 0 1 40.18 0 1 0 1 1 0 1 23.05 1 1 0 1 1 0 0 39.91 0 1 0 1 1 0 0 22.78 1 1 0 1 0 1 1 39.65 0 1 0 1 0 1 1 22.51 1 1 0 1 0 1 0 39.38 0 1 0 1 0 1 0 22.24 1 1 0 1 0 0 1 39.11 0 1 0 1 0 0 1 21.98 1 1 0 1 0 0 0 38.84 0 1 0 1 0 0 0 21.71 1 1 0 0 1 1 1 38.57 0 1 0 0 1 1 1 21.44 1 1 0 0 1 1 0 38.31 0 1 0 0 1 1 0 21.17 1 1 0 0 1 0 1 38.04 0 1 0 0 1 0 1 20.91 1 1 0 0 1 0 0 37.77 0 1 0 0 1 0 0 20.64 1 1 0 0 0 1 1 37.50 0 1 0 0 0 1 1 20.37 1 1 0 0 0 1 0 37.24 0 1 0 0 0 1 0 20.10 1 1 0 0 0 0 1 36.97 0 1 0 0 0 0 1 19.83 1 1 0 0 0 0 0 36.70 0 1 0 0 0 0 0 19.57 1 0 1 1 1 1 1 36.43 0 0 1 1 1 1 1 19.30 1 0 1 1 1 1 0 36.17 0 0 1 1 1 1 0 19.03 1 0 1 1 1 0 1 35.90 0 0 1 1 1 0 1 18.76 1 0 1 1 1 0 0 35.63 0 0 1 1 1 0 0 18.50 1 0 1 1 0 1 1 35.36 0 0 1 1 0 1 1 18.23 1 0 1 1 0 1 0 35.09 0 0 1 1 0 1 0 17.96 1 0 1 1 0 0 1 34.83 0 0 1 1 0 0 1 17.69 1 0 1 1 0 0 0 34.56 0 0 1 1 0 0 0 17.43 1 0 1 0 1 1 1 34.29 0 0 1 0 1 1 1 17.16 1 0 1 0 1 1 0 34.02 0 0 1 0 1 1 0 16.89 1 0 1 0 1 0 1 33.76 0 0 1 0 1 0 1 16.62 1 0 1 0 1 0 0 33.49 0 0 1 0 1 0 0 16.35 1 0 1 0 0 1 1 33.22 0 0 1 0 0 1 1 16.09 1 0 1 0 0 1 0 32.95 0 0 1 0 0 1 0 15.82 1 0 1 0 0 0 1 32.69 0 0 1 0 0 0 1 15.55 1 0 1 0 0 0 0 32.42 0 0 1 0 0 0 0 15.28 1 0 0 1 1 1 1 32.15 0 0 0 1 1 1 1 15.02 1 0 0 1 1 1 0 31.88 0 0 0 1 1 1 0 14.75 1 0 0 1 1 0 1 31.61 0 0 0 1 1 0 1 14.48 1 0 0 1 1 0 0 31.35 0 0 0 1 1 0 0 14.21 1 0 0 1 0 1 1 31.08 0 0 0 1 0 1 1 13.94 1 0 0 1 0 1 0 30.81 0 0 0 1 0 1 0 13.68 1 0 0 1 0 0 1 30.54 0 0 0 1 0 0 1 13.41 1 0 0 1 0 0 0 30.28 0 0 0 1 0 0 0 13.14 1 0 0 0 1 1 1 30.01 0 0 0 0 1 1 1 12.87 1 0 0 0 1 1 0 29.74 0 0 0 0 1 1 0 12.61 1 0 0 0 1 0 1 29.47 0 0 0 0 1 0 1 12.34 1 0 0 0 1 0 0 29.20 0 0 0 0 1 0 0 12.07 1 0 0 0 0 1 1 28.94 0 0 0 0 0 1 1 11.80 1 0 0 0 0 1 0 28.67 0 0 0 0 0 1 0 11.54 1 0 0 0 0 0 1 28.40 0 0 0 0 0 0 1 11.27 1 0 0 0 0 0 0 28.13 0 0 0 0 0 0 0 11.00
TC62D776CFNAG 2011-12-14 13 r, s, t, u setting (setting of test mode) r, s, t, u[0] setting of test mode 0 normal operation mode. (default after power-on) 1 test mode. h setting (setting of initialization h[0] setting of initialization 0 normal operation mode (default after power-on) 1 initializes all the internal data of the ic. after initialization, the tc62d776cfna g returns to normal operation mode. l setting (setting of standby mode (1)) l[0] setting of standby mode (1) 0 normal operation mode (default after power-on) 1 standby mode disables all circuits except digital logic, reducing the supply current of the ic. (all data in the TC62D776CFNAG is retained, and data can be loaded into the TC62D776CFNAG.) loading the s0 command in standby mode causes the TC62D776CFNAG to return to normal operation mode.
TC62D776CFNAG 2011-12-14 14 s3 command (input of state setting data (2).) description if sck pulses high nine or ten times while trans is high, it is interpreted as the s3 command, which acts as follows. the TC62D776CFNAG transfers the stat e control data (2) from the 16-bit shift register to the state control register. the states that can be programmed with the s3 command are shown below. basic input pattern of s3 command) sck trans sin sout (in case of j0=0) d15 c0 d14 d0 d13 e0 d12 f0 d11 g0 d10 i0 d9 j0 d8 k0 d7 m0 d6 n0 d5 o0 d4 p0 d3 q0 d2 - d1 - d0 - previous data d14 d13 d12 d15 command execution previous data 2 910 d14 d13 d15 57 3 68 4 sout (in case of j0=1) input form of state setting data (2) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c0 d0 e0 f0 g0 i0 j0 k0 m0 n0 o0 p0 q0 - - - *input in msb first. *please input "l" data to d8~d0. state setting data (2) setting input data setting bit outline of command 0 1 default after power-on c0 setting of thermal shutdown function (tsd) active not active active d0 setting of output open detection function (ood) not active active not active e0 setting of output short detection function (osd) not active active not active f0 setting of standby mode (2) normal operation active normal operation g0 setting of output short detection voltage v osd1 v osd2 v osd1 i0 setting of output delay function of output terminal active not active active j0 setting of sck trigger of sout up down up k0~q0 test mode setting. please input "l" data. "l"
TC62D776CFNAG 2011-12-14 15 details of each setting c setting (setting of thermal shutdown function (tsd)) c[0] setting of thermal shutdown function 0 enables thermal shutdown. (default after power-on) 1 disables thermal shutdown. d setting (setting of output open detection function (ood)) d[0] setting of output open detection function 0 disables output error detection. (default after power-on) 1 enables output error detection. e setting (setting of output short detection function (osd)) e[0] setting of output short detection function 0 disables output error detection. (default after power-on) 1 enables output error detection. f setting (setting of standby mode (2)) f[0] setting of standby mode (2) 0 normal operation mode. (default after power-on) 1 pre standby mode. condition 1: enters standby mode when t he contents of the latch become all-0s in normal operation mode. this disables all circuits except digi tal logic, reducing the supply current of the ic.(all data in the TC62D776CFNAG is retained, and data can be loaded into the TC62D776CFNAG.) condition 2: other than condition 1 the TC62D776CFNAG operates the same way as normal operation mode. g setting (setting of output short detection voltage) g[0] setting of output short detection voltage 0 v osd1 (default after power-on) 1 v osd2 i setting (setting of output delay function of output terminal) i[0] setting of output delay function of output terminal 0 disables output delay function. (default after power-on) 1 enables output delay function. j setting (setting of sck trigger of sout) j[0] setting of sck trigger of sout 0 data output trigger of sout is up edge of sck (default after power-on) 1 data output trigger of sout is down edge of sck k,m,n,o,p,q setting (setting of test mode) k,m,n,o,p,q[0] setting of test mode 0 normal operation mode. (default after power-on) 1 test mode.
TC62D776CFNAG 2011-12-14 16 thermal shutdown function (tsd) if the internal temperature of the ic exceeds 150 c, the thermal shutdown (tsd) circuitry trips, turning off all constant-current outputs. when the temperatur e drops below the tsd release threshold, the TC62D776CFNAG restarts constant-current output. since tsd is not intended to protect the ic against per manent damage. it should not be employed actively to monitor chip temperature. output delay function in order to reduce di/dt caused by simultaneously sw itching outputs, the TC62D776CFNAG allows for delays (t dly (on) , t dly (off) ) between contiguous outputs. switching time difference between outpu ts are provided in order as follows; 0out 15out 7out 8out 1out 14out 6out 9out 2out 13out 5out 10out 3out 12out 4out 11out power on reset function (por) the TC62D776CFNAG provides a power-on reset to reset all internal data in order to prevent malfunctions. the por circuitry works properly only when v dd rises from 0 v. to re-activate the por circuitry, v dd must be brought to less than 0.1 v. internal data is guaranteed to be retained after v dd exceeds 3.0 v. v dd waveform por workin g ran g e beyond por working range por working range v dd =2.8 v v dd =0.1 v v dd =0 v end of por v dd voltage for end of reset v dd =3.0v v dd voltage for guaranteed data
TC62D776CFNAG 2011-12-14 17 absolute maximum ratings (ta = 25c) characteristics symbol rating unit supply voltage v dd 6.0 v output current i out 95 ma logic input voltage v in ? 0.3~v dd + 0.3 (note 1) v output voltage v out ? 0.3 to 17 v operating temperature t opr ? 40 to 85 c storage temperature t stg ? 55 to 150 c thermal resistance r th(j-a) 80.07 c/w power dissipation p d 1.56 (notes 2) w note 1: however, do not exceed 6.0 v. note 2: power dissipation is reduced by 1/r th (j-a) for each c above 25c ambient. operating ranges (unless otherwise specified, v dd = 3.0 to 5.5 v, ta = ? 40c to 85c) characteristics symbol test conditions min typ. max unit supply voltage v dd ? 3.0 ? 5.5 v high level logic input voltage v ih test terminal are sin, sck, trans, enable 0.7 v dd ? v dd v low level logic input voltage v il test terminal are sin, sck, trans, enable gnd ? 0.3 v dd v high level sout output current i oh ? ? ? ? 1 ma low level sout output current i ol ? ? ? 1 ma constant current output i out test terminal is outn 1.5 ? 90 ma
TC62D776CFNAG 2011-12-14 18 ac characteristics (unless otherwise noted, v dd = 5.0 v, t a = 25 c) characteristics symbol test conditions min typ. max unit serial data transfer frequency f sck cascade connect ? ? 25 mhz sck pulse width t wsck sck=?h? or ?l? 20 ? ? ns trans pulse width t wtrans trans=?h? 20 ? ? ns enable pulse width t wena enable =?h? or ?l?, r ext =200 ? ~12 k ? 25 ? ? ns t setup1 test terminal are sin-sck 1 ? ? serial data setup time t setup2 test terminal are trans-sck 5 ? ? ns t hold1 test terminal are sin-sck 3 ? ? serial data hold time t hold2 test terminal are trans-sck 7 ? ? ns ac characteristics (unless otherwise noted, v dd = 3.3 v, t a = 25 c) characteristics symbol test conditions min typ. max unit serial data transfer frequency f sck cascade connect ? ? 25 mhz sck pulse width t wsck sck=?h? or ?l? 20 ? ? ns trans pulse width t wtrans trans=?h? 20 ? ? ns enable pulse width t wena enable =?h? or ?l?, r ext =200 ? ~12 k ? 25 ? ? ns t setup1 test terminal are sin-sck 1 ? ? serial data setup time t setup2 test terminal are trans-sck 5 ? ? ns t hold1 test terminal are sin-sck 3 ? ? serial data hold time t hold2 test terminal are trans-sck 7 ? ? ns
TC62D776CFNAG 2011-12-14 19 electrical characteristics (unl ess otherwise specified, v dd = 5.0 v ,ta = 25c) characteristics symbol te s t circuit test conditions min typ. max unit high level sout output voltage v oh 1 i oh = ? 1ma v dd ? 0.3 ? v dd v low level sout output voltage v ol 1 t a =-40~+85 c i ol = + 1ma gnd ? 0.3 v high level logic input current i ih 2 v in = v dd test terminal are enable , sin, sck ? ? 1 a low level logic input current i il 3 v in = gnd test terminal are sin, sck, trans ? ? -1 a i dd1 4 stand-by mode, v out =1v, sck=?l? ? ? 1.0 a power supply current i dd2 4 v out =1.0v, r ext =1.2k , all output off ? ? 7.0 ma constant current error (ic to ic) (s rank) i out(ic) 5 v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1.0 1.5 % constant current error (ch to ch) (s rank) i out(ch) 5 v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1.0 1.5 % constant current error (ic to ic) (n rank) i out(ic) 5 v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1.0 2.5 % constant current error (ch to ch) (n rank) i out(ch) 5 v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1.0 2.5 % output off leak current i ok 5 v out =17v, r ext =1.2k , outn off ? ? 0.5 a constant current output power supply voltage regulation %v dd 5 v dd =4.5~5.5v, v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1 5 %/v constant current output output voltage regulation %v out 5 v out =1.0~3.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 0.1 0.5 %/v pull-up resistor r (up) 3 test terminal is enable 240 300 360 k pull-down resistor r (down) 2 test terminal is trans 240 300 360 k ood voltage v ood 7 r ext =200 ? ~12k ? 0.2 0.3 0.4 v v osd1 7 r ext =200 ? ~12k ? v dd ? 1.3 v dd ? 1.4 v dd ? 1.5 osd voltage v osd2 7 r ext =200 ? ~12k ? 0.5 v dd 0.525 v dd 0.55 v dd v tsd start temperature t tds(on) ? junction temperature 150 ? ? c return time of normal mode from shdn mode t on ? time until output current after it becomes the normal mode from shdn mode flows ? ? 30 s
TC62D776CFNAG 2011-12-14 20 electrical characteristics (unl ess otherwise specified, v dd = 3.3 v ,ta = 25c) characteristics symbol te s t circuit test conditions min typ. max unit high level sout output voltage v oh 1 i oh = ? 1ma v dd ? 0.3 ? v dd v low level sout output voltage v ol 1 t a =-40~+85 c i ol = + 1ma gnd ? 0.3 v high level logic input current i ih 2 v in = v dd test terminal are enable , sin, sck ? ? 1 a low level logic input current i il 3 v in = gnd test terminal are sin, sck, trans ? ? -1 a i dd1 4 stand-by mode, v out =1.0v, sck=?l? ? ? 1.0 a power supply current i dd2 4 v out =1.0v, r ext =1.2k , all output off ? ? 7.0 ma constant current error (ic to ic) (s rank) i out(ic) 5 v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1.0 1.5 % constant current error (ch to ch) (s rank) i out(ch) 5 v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1.0 1.5 % constant current error (ic to ic) (n rank) i out(ic) 5 v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1.0 2.5 % constant current error (ch to ch) (n rank) i out(ch) 5 v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1.0 2.5 % output off leak current i ok 5 v out =17v, r ext =1.2k , outn off ? ? 0.5 a constant current output power supply voltage regulation %v dd 5 v dd =3.0~3.6v, v out =1.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 1 5 %/v constant current output output voltage regulation %v out 5 v out =1.0~3.0v, r ext =1.2k , 0out ~ 15out , 1ch output on ? 0.1 0.5 %/v pull-up resistor r (up) 3 test terminal is enable 240 300 360 k pull-down resistor r (down) 2 test terminal is trans 240 300 360 k ood voltage v ood 7 r ext =200 ? ~12k ? 0.2 0.3 0.4 v v osd1 7 r ext =200 ? ~12k ? v dd ? 1.3 v dd ? 1.4 v dd ? 1.5 osd voltage v osd2 7 r ext =200 ? ~12k ? 0.5 v dd 0.525 v dd 0.55 v dd v tsd start temperature t tds(on) ? junction temperature 150 ? ? c return time of normal mode from shdn mode t on ? time until output current after it becomes the normal mode from shdn mode flows ? ? 30 s
TC62D776CFNAG 2011-12-14 21 switching characteristics (unl ess otherwise specified, v dd = 5.0v ,ta = 25c) characteristics symbol te s t circ uit test condition min typ. max unit sck -sout t pd1u 6 up edge trigger mode 6 16 30 sck -sout t pd1d 6 down edge trigger mode 2 12 16 enable - outn t pd2 6 r ext = 1.2k ? 30 40 propagation delay time trans- outn t pd3 6 enable = ?l? ? 30 40 output rise time t or 6 10% to 90% points of out0 to 15out voltage waveforms D 10 20 output fall time t of 6 90% to 10% points of out0 to 15out voltage waveforms D 10 20 t dly (on) 6 reference timing waveforms r ext = 1.2k 1 4 9 output delay time t dly (off) 6 reference timing waveforms r ext = 1.2k 1 4 9 ns switching characteristics (unl ess otherwise specified, v dd = 3.3 v ,ta = 25c) characteristics symbol te s t circ uit test condition min typ. max unit sck -sout t pd1u 6 up edge trigger mode 6 16 30 sck -sout t pd1d 6 down edge trigger mode 2 14 18 enable - outn t pd2 6 r ext = 1.2k ? 30 40 propagation delay time trans- outn t pd3 6 enable = ?l? ? 30 40 output rise time t or 6 10% to 90% points of out0 to 15out voltage waveforms D 10 20 output fall time t of 6 90% to 10% points of out0 to 15out voltage waveforms D 10 20 t dly (on) 6 reference timing waveforms r ext = 1.2k 2 6 12 output delay time t dly (off) 6 reference timing waveforms r ext = 1.2k 2 6 12 ns
TC62D776CFNAG 2011-12-14 22 test circuits test circuit 1: high level sout output voltage / low level sout output voltage test circuit 2: high level logic input current / pull-down resistor test circuit 3: low level logic input current / pull-up resistor vdd out0 15out c l = 10.5 pf a a a a v dd = 5v, 3.3v gnd sin trans sck enable r-ext sout vdd out0 c l = 10.5 pf v in = v dd a a a a v dd = 5.5 v, 3.3v gnd sin trans sck enable r-ext sout 15out vdd out0 gnd i o = ? 1 ma to 1 ma c l = 10.5 pf v dd = 5 v, 3.3v f. g v sin trans sck enable r-ext sout 15out
TC62D776CFNAG 2011-12-14 23 test circuit 4: supply current test circuit 5: constant current error(ic to ic) / constant current error(ch to ch) output off leak current constant current output power supply voltage regulation constant current output voltage regulation test circuit 6: switching characteristics c l i out vdd out0 15out c l = 10.5 pf f. g v dd = 5 v, 3.3v gnd sin trans sck enable r-ext sout v ih = v dd v il = 0 v t r = t f = 10 ns (10 to 90%) v l = 5 v c l = 10.5 pf r ext = 1.2 k r l =300? vdd out0 15out c l = 10.5 pf f. g a a v dd = 4.5 to 5.5 v, 3 to 3.6v gnd sin trans sck enable r-ext sout r ext = 1.2 k v out = 1v to 3v, 17v vdd 15out c l = 10.5 pf f. g a gnd sin trans sck enable r-ext sout out0 r ext = 1.2 k v out = 1v v dd = 5 v, 3.3v
TC62D776CFNAG 2011-12-14 24 test circuit 7: odd and osd voltage sck sin vdd out0 15out sout gnd r ext c l = 10.5 pf v dd = 5 v, 3.3v r ext = 200 ? , 12k f. g v out1 = 1v v v v trans enable v out2 all outputs are configured to be on. one output is connected to v ds2 , and the other outputs are connected to v ds1 .v ood and v osd are measured by changing v ds2 and monitoring the other output voltages and error detection results from sout.
TC62D776CFNAG 2011-12-14 25 timing waveforms 1. sck, sin, sout 2.trans, sout, enable , outn 3. outn outn are voltage waveform.
TC62D776CFNAG 2011-12-14 26 4. enable , outn outn are voltage waveform.
TC62D776CFNAG 2011-12-14 27 reference data the above data is for reference only, not guaranteed. careful evaluation is required prior to creating a production design. output current vs. external resistor this graph shows the characteristics per channel when all the outputs are on. i o - r ext 0 10 20 30 40 50 60 70 80 90 100 1000 10000 r ext () i o (ma) i out (ma) i out ? r ext t a =25 c v out =1v theoretical formula i out (a) = 1.03 (v) r ext ( )) 16.5
TC62D776CFNAG 2011-12-14 28 reference data the above data is for reference only, not guaranteed. careful evaluation is required prior to creating a production design. output current (i out ) ? output voltage (v out ) i out - v out v dd =3.3v,ta=25 ,1chon 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 v out (v) i out (ma) i out - v out v dd =5.0v,ta=25 ,1chon 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 v out (v) i out (ma)
TC62D776CFNAG 2011-12-14 29 notes on design of ics 1 decoupling capacitors between power supply and gnd it is recommended to place decoupling capacitors between power supply and gnd as close to the ic as possible. 2 output current setting resistors when the output current setting resistors (r ext ) are shared among multiple ics, production design should be evaluated carefully. 3 board layout ground noise generated by output switching might cause t he ic to malfunction if the ground line exhibits inductance and resistance due to pc board traces and wire leads. also, the inductance between the ic output pins and the led cathode pins might caus e large surge voltage, damaging leds and the ic outputs. to avoid this situation, pc board traces and wire leads should be carefully laid out. 4 consult the latest technical information for mass production.
TC62D776CFNAG 2011-12-14 30 package dimensions cfnag type p-ssop24-0409-0.64-001 unit : mm weight: 0.14 g (typ.)
TC62D776CFNAG 2011-12-14 31 notes on contents 1. block diagrams some of the functional blocks, circ uits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document ar e provided for reference purposes only. thorough evaluation is required, especially at the mass production design stage. toshiba does not grant any license to any industrial property rights by prov iding these examples of application circuits. 5. test circuits components in the test circuits are used only to obtain and confirm the devi ce characteristics. these components and circuits are not guaranteed to prev ent malfunction or failure from occurring in the application equipment. ic usage considerations notes on handling of ics the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or ic failure. th e ic will fully break down when us ed under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large cu rrent to continuously flow and the breakdown can lead smoke or ignition. to minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. if your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power on or the negative current resulting from the back electromotive force at power off. ic breakdown may cause injury , smoke or ignition. use a stable power supply with ics with built-in protec tion functions. if the power supply is unstable, the protection function may not operate, causing ic breakdown. ic breakdown may cause injury, smoke or ignition. do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative terminals of power supplies are connected properly. otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. in addition, do not use any device that is applied th e current with inserting in the wrong orientation or incorrectly even just one time. carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. if there is a large amount of leakage current such as input or negative feedback condenser, the ic output dc voltage will increase. if this output voltage is connected to a speaker with low input withstand voltage, overcurrent or ic failure can ca use smoke or ignition. (the over current can cause smoke or ignition from the ic itself .) in particular, please pay attention when using a bridge tied load (btl) connection type ic that inputs outp ut dc voltage to a speaker directly.
TC62D776CFNAG 2011-12-14 32 points to remember on handling of ics (1) over current prot ection circuit over current protection circuits (referred to as current limiter circuits) do not necessarily protect ics under all circumstances. if the ov er current protection circuits oper ate against the over current, clear the over current stat us immediately. depending on the method of use and usage condit ions, such as exceeding absolute maximum ratings can cause the over current protection circuit to not operate properly or ic breakdown before operation. in addition, depending on the method of use and usage conditions, if ov er current continues to flow for a long time after operation, the ic may generate heat resulting in breakdown. (2) back-emf when a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the motor?s power supply due to the effect of back-emf. if the current sink capability of the power supply is small, the device?s motor power supply and outp ut pins might be exposed to conditions beyond absolute maximum ratings. to avoid this problem, ta ke the effect of back-emf into consideration in system design. (3) thermal shutdown circuit thermal shutdown circuits do not necessarily protect ics under all circumstances. if the thermal shutdown circuits operate against the over temperature, clear the heat generation status immediately. depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the thermal shutdown circuit to not operate properly or ic breakdown before operation.
TC62D776CFNAG 2011-12-14 33 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collect ively ?toshiba?), reserve the right to make changes to the in formation in this document, and related hardware, software an d systems (collectively ?product?) without notice. ? this document and any information herein may not be reproduc ed without prior written permission from toshiba. even with toshiba?s written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product?s quality a nd reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for provid ing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid sit uations in which a malfunction or failure of product could cause loss of human life, b odily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, customers mu st also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications , the data sheets and application notes for product and the precautions and conditions set forth in the ?toshiba semiconduc tor reliability handbook? and (b) the instructio ns for the application with which the product will be used with or for. customers are solely responsible for all aspects of their own product design or applications, including but not lim ited to (a) determining the appropriateness of the use of this product in such des ign or applications; (b) evaluating and dete rmining the applicability of any information contained in this document, or in charts, dia grams, programs, algorithms, sample application circuits, or any other referenced document s; and (c) validating all operating paramete rs for such designs and applications. toshiba assumes no liability for customers? product design or applications. ? product is intended for use in general el ectronics applications (e.g., computers, personal equipment, office equipment, measur ing equipment, industrial robots and home electroni cs appliances) or for specif ic applications as expre ssly stated in this document . product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality a nd/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or se rious public impact (?unintended use?). unintended use includes, without limit ation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equi pment used for automobiles, trains, ships and other transportation, traffic signalin g equipment, equipment used to control combustions or explosions, safety devices, elevat ors and escalators, devices related to el ectric power, and equipment used in finance-related fi elds. do not use product for unintended us e unless specifically permitted in thi s document. ? do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy product, whether in whole or in part. ? product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no re sponsibility is assumed by toshiba for an y infringement of patents or any other intellectual property rights of third parties that may result from the use of product. no license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. ? absent a written signed agreement, except as provid ed in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, co nsequential, special, or incidental damages or loss, including without limitation, loss of profit s, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or conditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? do not use or otherwise make available product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpil ing or manufacturing of nucl ear, chemical, or biological weapons or missile technolog y products (mass destruction weapons). product and related softwa re and technology may be controlled under the japanese foreign exchange and foreign trade law and the u.s. export administration r egulations. export and re-export of product or related softw are or technology are strictly prohibited except in comp liance with all applicable export laws and regulations. ? please contact your toshiba sales representative for details as to environmental matters such as the rohs compatibility of pro duct. please use product in compliance with all applicable laws and regula tions that regulate the inclusion or use of controlled subs tances, including without limitation, the eu rohs directive. toshiba assumes no liability for damages or losses occurring as a result o f noncompliance with applicable laws and regulations.

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